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TV-Stereo-Surround Sound Interface IC
TDA 6811
Preliminary Data
Bipolar IC
Features The TDA 6811 contains I2C Bus controlled functions, which are required as a supplement to a Dolby surround sound audio system. The circuit is divided into two functional blocks: High-Quality Sound Processing
q Fine-step stereo level control for adjustment
of the Dolby(R) decoder q Volume control for the rear channel Control Circuit
q I2C Bus interface q Control of AF sound processing q Switch outputs (seven)
P-DIP-18-1
Type TDA 6811
Ordering Code Q67000-A5145
Package P-DIP-18-1
Dolby(R) is a registered trademark of Dolby Laboratories Corporation. Purchase of Siemens I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips.
Semiconductor Group
1
08.93
TDA 6811
Signal Circuit The integrated circuit contains the components required for extending a conventional stereo sound system from a two-channel arrangement to a three-channel Dolby surround system with Dolby decoder. The first component is a fine-step two-channel AF-level controller. It is used for adjusting the Dolby decoder. Its operating range is 3 dB with 0.2 dB steps. The left and right channels can be adjusted separately. The second component, a mono volume control with a maximum gain of 10 dB, is used for the rear channel generated in the Dolby decoder. 56 steps of 1.25 dB each provide a control range of 68.75 dB. A total of seven switch outputs are provided for controlling the Dolby decoder via the I2C Bus. Control Circuit An I2C Bus interface with listen/talk action controls all functions. The currently valid data are stored in a latch block. The telegram structure is as follows: Start condition - chip address - any number of data bytes - stop condition. The following conditions apply to data bytes: The actual data byte (containing the data information) must always be preceded by a subaddress byte. Various subaddresses can be accessed within a message (ie. without new start condition).
Chip Address MSB 1 . 0 . 0 . 1 . 0 . 0 . 1 LSB 0
Subaddress Bytes MSB Fine adjust, left Fine adjust, right Volume control Switch outputs X X X X . X X X X . X X X X . X X X X . 0 0 0 0 . 0 0 0 0 . 0 0 1 1 LSB 0 1 0 1
Semiconductor Group
2
TDA 6811
a) Volume Control MSB Maximal volume Max - 1 Max - 15 Max - 55 MUTE Power ON X X X X X 0 . X X X X X 0 . 1 1 1 0 0 0 . 1 1 1 0 0 0 . 1 1 0 1 0 0 . 1 1 0 0 X 0 . 1 1 0 0 X 0 LSB 1 0 0 0 X 1
b) Fine Adjust Left/Right MSB Maximal gain Max - 1 Gain 0 dB Minimum gain Minimum gain Power ON X X X X X X . X X X X X X . X X X X X X . 1 1 1 0 0 0 . 1 1 0 0 0 0 . 1 1 0 0 0 0 . 1 1 0 0 0 0 LSB 1 0 0 1 X 1
c) Switch Byte MSB P7 P1 P1 P2 P2 P3 P3 P4 P4 P5 P5 P6 P6 P7 P7 = = = = = = = = = = = = = = 0 1 0 1 0 1 0 1 0 1 0 1 0 1 . P6 . P5 . P4 . P3 . P2 . P1 LSB X
Port 1 (open collector) low (low-impedance); power ON Port 1 high (high-impedance) Port 2 (open collector) low (low-impedance); power ON Port 2 high (high-impedance) Port 3 (open collector) low (low-impedance); power ON Port 3 high (high-impedance) Port 4 (open collector) low (low-impedance); power ON Port 4 high (high-impedance) Port 5 (open collector) low (low-impedance); power ON Port 5 high (high-impedance) Port 6 (open collector) low (low-impedance); power ON Port 6 high (high-impedance) Port 7 (open collector) low (low-impedance); power ON Port 7 high (high-impedance)
Semiconductor Group
3
TDA 6811
Block Diagram Semiconductor Group 4
TDA 6811
Pin Configuration (top view)
Semiconductor Group
5
TDA 6811
Pin Functions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Symbol FADIL Bias FADIR GND SDA SCL Function Fine adjust input left Bias for AF operation Fine adjust input right Ground I2C Bus SDA I2C Bus SCL Supply voltage + VS Volume control input Volume control output Switch output 7 Switch output 6 Switch output 5 Switch output 4 Switch output 3 Switch output 2 Switch output 1 Fine adjust output right Fine adjust output left
VS
VOL IN VOL OUT
V7 V6 V5 V4 V3 V2 V1
FADOR FADOL
Semiconductor Group
6
TDA 6811
Pin Description
AF Inputs (Pin 1/3/8)
Bias for AF Operation Point (Pin 2) Semiconductor Group 7
TDA 6811
I2C Bus SDA (Pin 5)
I2C Bus SCL (Pin 6)
Semiconductor Group
8
TDA 6811
Port Outputs (Pin 10-16)
AF Outputs (Pin 9/17/18)
Semiconductor Group
9
TDA 6811
Absolute Maximum Ratings TA = 0 to 70 C Parameter Supply voltage Max. DC voltage Max. DC voltage Max. DC voltage Max. DC voltage Max. DC current Max. DC current Max. DC current Max. DC current Max. DC current Max. DC current Max. DC current Max. DC current Max. DC current Max. DC current Max. DC current ESD voltage Junction temperature Storage temperature Termal resistance (system-air) Operating Range Supply voltage Ambient temperature Input frequency range Symbol Limit Values min. max. 14 V V V V V mA mA mA mA mA mA mA mA mA mA mA kV C C K/W HBM (R = 1.5 k, C = 100 pF) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -2 - 40 Unit Remarks
V7 V1 V2 V6 V8 I5 I9 I10 I11 I12 I13 I14 I15 I16 I17 I18 VESD Tj Tstg Rth SA
V7 V7 V7 V7
3 2 3 3 3 3 3 3 3 2 2 2 150 125 68
VS TA fI
10 0 0.01
13.2 70 20
V C kHz
Semiconductor Group
10
TDA 6811
AC/DC Characteristics VS = 12 V; TA = 25 C, in accordance with test circuit I2C Bus preset: start-92-00, 10 - 01, 0 - 02, 3F - 03, FE Adr. Fine adjust lin., Vol. max, Ports high The basic setting for each point in the specification is always preset; only settings which are deviate from this, are given in the test conditions. Detail in italics only provide explanation of the hexadecimal code and which switch bits on the setbytes are stated. AF reference level 0 dB = 300 mV, if not different defined. fI 20 Hz - 20 kHz Parameter Current consumption Signal Section Volume control Max. gain Min. gain Volume step width Max. input voltage Max. output voltage Distortion factor Unweighted signal/ noise ratio Noise voltage Attenuation MUTE DC jump 1 bit Fine adjustment Max. gain Max. gain Max. gain Max. gain Adjust step width Adjust step width Symbol min. Limit Values typ. 17 max. mA Unit Test Condition
I7
G9-8 G9-8 G9 V8 V9 THD9 aS/N9 VN9 a9-8 V9
80 90 2 2.2
10 - 58.75 55 1.25 2.5
dB dB dB
02, 10, Vol 8 02, X - 02, (X 1) Vol X - Vol (X 1)
Vrms THD9 < 1% Vrms THD9 < 1%; 02, X; any setting 0.01 97 15 30 6 0.05 % dB V dB mV
V8 = 300 Vrms V8 = 600 mVrms
02, 10, Vol 8 02, 00, MUTE 02, X - 02, (X 1) Vol X - Vol (X 1) 00, 1 F, AdjI 31 01, 1 F, Adjr 31 00, 01, AdjI 1 01, 01, Adjr 1 00, X - 00, (X 1) AdjI X - AdjI, (X 1) 01, X - 01, (X 1) Adjr X - Adjr, (X 1)
G18-1 G17-3 G18-1 G17-3 G18 G17
2.5 2.5 - 3.5 - 3.5
3 3 -3 -3
3.5 3.5 - 2.5 - 2.5 0.2 0.2
dB dB dB dB dB dB
Semiconductor Group
11
TDA 6811
AC/DC Characteristics (cont'd) VS = 12 V; TA = 25 C, in accordance with test circuit Parameter Max. input voltage Max. input voltage Max. output voltage Max. output voltage Distortion factor Distortion factor Unweighted signal/ noise ratio Unweighted signal/ noise ratio DC jump 1 bit DC jump 1 bit PSRR (Power Supply Ripple Rejection) Symbol min. Limit Values typ. max. Vrms 00, X; any setting Vrms 01, X; any setting Vrms 01, X; any setting Vrms 00, X; any setting 0.01 0.01 97 97 4 4 70 70 70 0.05 0.05 % % dB dB mV mV dB dB dB 1.4 1.4 2 2 Unit Test Condition
V1 V3 V17 V18 THD17 THD18 aS/N17 aS/N18 V17 V18 aPSRR9 aPSRR17 aPSRR18
V3 = 300 mVrms V1 = 300 mVrms V3 = 600 mVrms V1 = 600 mVrms
01, X - 01, (X 1) Adjr X - Adjr, (X 1) 00, X - 00, (X 1) AdjI X - AdjI, (X 1)
VI interf. = 1 Vrms fI interf. = 50 Hz - 20 kHz RG = 220
unweighted
Design Hints Input resistance Input resistance Input resistance Output resistance Output resistance Output resistance
R1 R3 R8 R9 R17 R18
30 30 30 70 70 70
k k k
Semiconductor Group
12
TDA 6811
AC/DC Characteristics (cont'd) Parameter Symbol Limit Values min. I2C Bus (SCL, SDA) Pulse edges SCL, SDA Rise time Decay time Clock SCL Frequency H-pulse width L-pulse width Start Set-up time Hold time Stop Set-up time Bus free Data transfer Set-up time Hold time Inputs SCL, SDA Input voltage typ. max. Unit Test Condition
tR tF fSCL tHIGH tLOW tSUSTA tHDSTA tSUSTO tBUF tSUDAT tHDDAT VQH VQL IQH IQL VQH VQL VH VL
5.4 0 4 4 4 4 4 4 1 300 3
1 300 100
s ns kHz s s s s s s s ns
5.5 1,5 50 100
V V A A V V V V
Input current Output SDA (open collector) Output voltage
0.4
RL = 2.5 IQL= 3 mA RL = 4 IQL= 3 mA
Output voltage Port
VS
0.4
Semiconductor Group
13
TDA 6811
Test Circuit Semiconductor Group 14
TDA 6811
Application Circuit 1 Semiconductor Group 15
TDA 6811
Application Circuit 2 Semiconductor Group 16
TDA 6811
I2C Bus Timing Diagram
tSUSTA tHDSTA tHIGH tLOW tSUDAT tHDDAT tSUSTO tBUF tF tR
Set-up time (start) Hold time (start) HIGH pulse width (clock) LOW pulse width (clock) Set-up time (data transfer) Hold time (data transfer) Set-up time (stop) Bus free time Fall time Rise time
All times are referenced to the VIH and VIL values.
Semiconductor Group
17
TDA 6811
Plastic Package, P-DIP-18-1 (Plastic Dual-in-Line Package)
Sorts of Packing Package outlines for tubes, trays ect. are contained in our Data Book "Package Information"
Dimensions in mm
Semiconductor Group
18

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